Native UALink switch ASICs announced as samplingno data
— count
on track <= 1 · off >= 2manual ↗
connector returned no usable reading · checked 2026-09-07
Radar · Networking fabric · T1 · 2027 · WARNING
No UALink Consortium member announces general availability or volume production of a switch ASIC implementing the native UALink 200G specification (not an Ethernet-tunnelled or bridged variant) on or before 2027-12-31.
Scale-up fabric is where NVLink's moat lives. Until a native UALink switch ships in volume, every non-NVIDIA accelerator rack is bridged over Ethernet with a latency and power penalty, which caps how fast custom silicon can take share. Rack power density and cabling design for 2028 buildings depend on which fabric actually exists.
Registered at 50% on September 8, 2026. Engine repriced 2 times; now 47%.
Registered thresholds. Status is computed from the latest public reading.
Native UALink switch ASICs announced as samplingno data
— count
on track <= 1 · off >= 2manual ↗
connector returned no usable reading · checked 2026-09-07
Second non-Broadcom vendor cites 1.6T or CPO hyperscaler design winno data
— boolean
on track == 0 · off == 1manual ↗
connector returned no usable reading · checked 2026-09-07
Would raise my number
Would cut it
6 personas on one model (openai/gpt-5.6-sol); other vendors were unavailable this run, so read this as one model's persona-averaged view.
43%
grid-and-power-planner · openai/gpt-5.6-sol
Reference class: new data-center switch ASICs moving from sampling to production, where 12–24 months is common but schedule slippage is frequent. Nearly 16 months remain. I move below the 0.50 structural prior for HIT because the consortium roadmap targets products in 2027, multiple members create several chances for a qualifying announcement, and issuing that announcement is inexpensive once production starts. I retain substantial HIT probability because native UALink is a new fabric, announced deployments remain bridged, sampling evidence is unverified here, and qualification, software, packaging, or system-readiness delays could push production beyond 2027. The no-data indicators add no readiness evidence. Against-forecaster ambiguity modestly reduces HIT probability.
43%
semiconductor-supply-chain-analyst · openai/gpt-5.6-sol
Reference class: first-generation interconnect switch ASICs typically require roughly 4–8 quarters from sampling through qualification and production, with frequent one-to-two-quarter slips. About five quarters remain, so any single programme could miss. However, the falsifier needs only one Consortium member to issue a qualifying announcement, and the supplied roadmap already targets products in 2027. Multiple potential vendors plus the low threshold of a production-status press release make a MISS slightly more likely than a HIT. Continued bridge-based deployments and absent indicator data preserve substantial slippage risk; strict, ambiguity-against-forecaster resolution also trims the HIT probability.
46%
enterprise-cio · openai/gpt-5.6-sol
My reference class is sampled networking switch ASICs with a public next-year product roadmap. I assign roughly a 0.44 annual hazard of a qualifying GA or volume announcement; over 15.8 months, compounding gives about 0.47 survival. The native-UALink requirement and current reliance on Ethernet bridges support slippage: silicon qualification, packaging, firmware, and customer validation often exceed a year. Conversely, the consortium targeted 2027 products, multiple members can trigger resolution, and a vendor need only publish qualifying production language—not prove broad deployment. Ambiguity against the forecaster trims my estimate to 0.46, below the stated 0.50.
45%
credit-analyst · openai/gpt-5.6-sol
I use sampled interconnect ASICs progressing to production announcements within 12–24 months as the reference class. A roughly 0.55 annual qualifying-announcement hazard over the remaining 15.8 months implies survival near 0.48. The consortium’s stated 2027 product target and multiple potential member vendors increase the chance that at least one issuer prints production language. Offsetting that, native fabrics commonly slip, and the rule excludes sampling, demonstrations, design wins, and Ethernet bridges while requiring an explicit member or consortium announcement. I therefore place the HIT probability slightly below the forecaster’s 0.50.
44%
geopolitics-policy-analyst · openai/gpt-5.6-sol
I use the reference class of sampled data-center switch ASICs approaching a publicly targeted product year: many reach production within 12–18 months, but schedule slips, qualification cycles, and ecosystem dependencies are common. Roughly 16 months remain, and multiple consortium members create several opportunities for a qualifying announcement. Conversely, the rule requires native UALink 200G silicon and explicit GA or production-shipping language; bridge products, demonstrations, and sampling do not count. The absence of usable leading-indicator data prevents raising confidence. The cheapness of issuing a production press release and ambiguity resolving against the forecaster put HIT modestly below even odds.
46%
superforecaster-statistician · openai/gpt-5.6-sol
Base rate: I use the supplied 0.50 reference-class prior for hard-date disclosure questions, implying roughly a 0.41 annual hazard of a qualifying announcement over the remaining 15.8 months. Sampling status and a public roadmap targeting products in 2027 raise that hazard, while multiple consortium members provide several opportunities to falsify this universal-negative claim. Conversely, the resolution requires native—not bridged—silicon and specific production language on an official site; actual shipment without that disclosure would not count. Missing indicators add no evidence. Ambiguity resolving against the forecaster trims the HIT probability further. No calibration table was supplied for an additional correction.
50% from reference-class:qtype:disclosure. ledger base rate, n=29, horizon 480d; the ledger has no multi-year history